When time sensitive data, such as voice or video, is transported over asynchronous packet networks, such as Ethernet networks, some method must be employed to regenerate the local clock at the far end. Currently, several methods exist for transmitting clock signals over a packet network. Such methods include using a duplex connection and assuming that the delay over the packet network is more or less symmetrical, averaging the delay in a simplex connection, and using a detection mechanism in which each receiving node detects a shared event.
Not many methods are described that optimize the performance of such an approach over a large number of networks. If the number of networks grows, the number of potential problems increases dramatically. The likelihood of problems arising typically grows according to an exponential curve as the number of networks increases.
In a complex packet network environment it is not trivial to transport clock signals. Clocks are physical signals that exist in absolute time, and packet networks are designed to have as little time dependency as possible. The lack of real time performance in complex packet networks can reach such complex behavior that it becomes nearly impossible to perform acceptable clock recovery. The delay variation in a complex packet network, from input to output, typically becomes larger for each ‘hop’.
Pending standard IEEE 1588 discloses a “divide and conquer” approach that uses ‘boundary clocks’. These clocks are intended to cross the boundary between subdomains in such a way that the normal element that connects these sub-domains, routers, does not contribute to the delay. In the standard this is contrasted relative to the switches, where no such boundary clock is necessary.
According to the IEEE standard this is related to the fact that the switches have much smaller delay times than the routers. While that may have once been true, modern routers have a performance comparable with that of switches, and both introduce delays which in modern telecomm environments are considered to be quite large, albeit not as large as older routers. As such the suggested approach in the IEEE 1588 standard does not allow for the fact that a complex packet network, consisting only of multiple switches, can still introduce delay problems, nor does the standard describe what should be done at the boundary clock, except minimizing the delays by making the timepath shorter.
The problem of concatenated switches and routers is that the likelihood of timing traffic passing without severe delays becomes ever smaller. If in a simplified model the traffic density is assumed to be constant, the actual delay experienced by a packet traversing the networks is a function of the number of delay elements or hops. The actual delay is a concatenation of delays, such as the delay due to protocol stack handling (both on sending and receiving side), input queuing in the switch, output queuing in the switch, other administrative tasks (both in sending side, receiving side and switch), possibly contention and such. It is acceptable in the simple approach to assume constant average traffic density over all nodes, and later assess performance around bottlenecks in the system.
It is known to perform clock recovery in an intermediate node to extract physical signals for use in the physical domain at the intermediate node.